1. Technical Field
The present invention relates to a wafer level semiconductor package, and more particularly, to a new semiconductor package with small size and enhanced durability.
2. Discussion of the Related Art
In a wafer level packaging process, a wafer with integrated circuit deposited therein or chips mounted thereon undergoes a series process, such as die-bonding, molding, marking and so on, and is finally cut into finished products. Wafer level packaging process has been considered as suitable technology for small sized and high speed package.
Especially, chip-size package realized in wafer level process enables a single memory module to have much more chips mounted thereon, so as to easily fabricate a mass storage memory module.
Moreover, a semiconductor device fabricated with wafer level packaging technology has enhanced electrical property and good heat radiation because of short length to an outer connection part (ex. an outer bump). Thus, wafer level packaging technology can improve remarkably the quality and reliability of a semiconductor device.
Referring to FIG. 1, a plurality of active areas (110) with integrated circuit thereon is arranged apart from each other in the surface of a semiconductor wafer (100). In wafer level semiconductor packaging process, every packaging step is processed on a wafer with uncut active areas, and the wafer is cut into single packages in final step. The active areas (110) may include thin film elements, such as transistor, metal pattern, or passive device, and additional semiconductor chip mounted thereon. In this case, the wafer functions as a base substrate (or support body) for packaging a semiconductor chip. After a semiconductor chip (not shown) is mounted on the wafer by flip-chip bumping or die-attach, a molding layer (300) is formed on the chip all over the wafer, as shown in FIG. 2. In this manner, forming a large sized molding layer at a wafer level enables a semiconductor packaging process to be more effective.
However, large sized molding layer formed at a wafer level is inevitably under stress due to a difference of CTE (coefficient of thermal expansion) or Young's modulus between the wafer and the molding layer. FIG. 3 shows schematically the stress generated in molding layer. The stress creates a compressive force in the direction to the center from the outside (direction of the arrow). Resultantly, concave type warpage is generated in the wafer as shown in FIG. 4.
The warpage of a wafer brings about compatibility problem in using the equipments for packaging process, and thus the following process such as grinding or testing is impossible. Warpage issue is serious especially in a large sized wafer, and has raised an obstacle to a wafer level semiconductor packaging process.
Accordingly, in order to guarantee the process reliability of wafer level packaging technology and fabricate durable semiconductor packages, there is many problems to be solved. Especially, a new technology of wafer level molding process is required for reducing the warpage of a wafer.
As another issue in a semiconductor package with semiconductor chips stacked therein, the contact area between different materials, for example between a semiconductor chip and a molding layer, has poor resistance to stress. In particular, crack or flaking due to thermal and mechanical stress is concentrated on the outside or corner of a package. The crack or flaking decreases physical durability of a package, and becomes more serious as the size of a package gets smaller.
Therefore, the present invention is directed to provide a new semiconductor package with reduced crack and flaking at the interface between a different material in a package to improve reliability.
Another object of the present invention is to provide a light, thin, short and small chip-sized package fabricated in a wafer level process.
Still another object of the present invention is to reduce a warpage of a wafer in a wafer level process, and is to provide with a semiconductor package with enhanced reliability.